TIME: A training-in-memory architecture for memristor-based deep neural networks
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Yu Wang | Huazhong Yang | Yuan Xie | Yi Cai | Ming Cheng | Lixue Xia | Zhenhua Zhu | Lixue Xia | Yu Wang | Huazhong Yang | Yuan Xie | Y. Cai | Ming Cheng | Zhenhua Zhu
[1] Shimeng Yu,et al. MNSIM: Simulation platform for memristor-based neuromorphic computing system , 2016, DATE 2016.
[2] Tao Zhang,et al. PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).
[3] Jian Sun,et al. Delving Deep into Rectifiers: Surpassing Human-Level Performance on ImageNet Classification , 2015, 2015 IEEE International Conference on Computer Vision (ICCV).
[4] Yu Wang,et al. MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Avinoam Kolodny,et al. Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training , 2015, IEEE Transactions on Neural Networks and Learning Systems.
[6] Shimeng Yu,et al. A neuromorphic visual system using RRAM synaptic devices with Sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling , 2012, 2012 International Electron Devices Meeting.
[7] Yann LeCun,et al. The mnist database of handwritten digits , 2005 .
[8] Shimeng Yu,et al. Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM) , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.
[9] Alex Graves,et al. Playing Atari with Deep Reinforcement Learning , 2013, ArXiv.
[10] Cong Xu,et al. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[11] Jia Wang,et al. DaDianNao: A Machine-Learning Supercomputer , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[12] Norman P. Jouppi,et al. Understanding the trade-offs in multi-level cell ReRAM memory design , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[13] Y. Leblebici,et al. Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power) , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).
[14] Tarek M. Taha,et al. Enabling back propagation training of memristor crossbar neuromorphic processors , 2014, 2014 International Joint Conference on Neural Networks (IJCNN).
[15] Shuchang Zhou,et al. DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients , 2016, ArXiv.
[16] Yu Wang,et al. Switched by input: Power efficient structure for RRAM-based convolutional neural network , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[17] Yann Le Cun,et al. A Theoretical Framework for Back-Propagation , 1988 .
[18] William J. Dally,et al. GPUs and the Future of Parallel Computing , 2011, IEEE Micro.
[19] Yu Wang,et al. Training itself: Mixed-signal training acceleration for memristor-based neural network , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).
[20] Yu Wang,et al. RRAM-Based Analog Approximate Computing , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.