Microprocessor Performance Evaluation

This Chapter illustrates the application of RIPE as a performance evaluation tool for existing and future single chip microprocessors. Two step-by-step examples demonstrate the capability of RIPE in predicting the performance of existing microprocessor systems. These specific examples were part of a set of designs used to benchmark the various RIPE models during their development. Based on RIPE’s modeling capability for existing designs, the tool is used to evaluate future system designs based on 1994 NTRS technology guidelines [1]. A similar RIPE analysis has also recently been completed for the 1997 NTRS with similar conclusions [2]. System and technology parameters are varied to evaluate design alternatives and their impact on system performance. The results show that improvement in interconnect materials alone will not be sufficient to reach the NTRS performance projections. Additional advancements in architecture, logic, circuit and layout design will be needed to bridge the future performance gap created by interconnect. Similarly, NTRS power dissipation guidelines will require innovative low power design techniques. Finally, RIPE is used to demonstrate the relationship between interconnect strategy, system wiring capacity and total die size. To put the NTRS projections in perspective, a comparison is made between the 1994 NTRS expectations for the 0.35 μm technology generation and the actual technology status.

[1]  P. Bannon,et al.  A 433 MHz 64 b quad issue RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  Gilbert Wolrich,et al.  A 300-MHz 64-b quad-issue CMOS RISC microprocessor , 1995 .

[3]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[4]  Paul S. Zuchowski,et al.  Technology-migratable ASIC library design , 1996, IBM J. Res. Dev..

[5]  Soha Hassoun,et al.  A 200-MHz 64-bit Dual-Issue CMOS Microprocessor , 1992, Digit. Tech. J..

[6]  William J. Bowhill,et al.  Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU , 1995, Digit. Tech. J..

[7]  R. Mangaser,et al.  Estimating interconnect performance for a new National Technology Roadmap for Semiconductors , 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).

[8]  Yuan Taur,et al.  A half-micron CMOS logic generation , 1995, IBM J. Res. Dev..

[9]  George A. Sai-Halasz,et al.  Directions in future high end processors , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[10]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[11]  C. G. Hsi,et al.  Figures of merit for system path time estimation , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.