Analysis of ground bounce in deep sub-micron circuits
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[1] R. Ghaffarian. Close the information gap on IC-package reliability , 1998 .
[2] Melvin A. Breuer,et al. Process aggravated noise (PAN): new validation and test problems , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[3] Malgorzata Marek-Sadowska,et al. Clock skew optimization for ground bounce control , 1996, ICCAD 1996.
[4] R. Senthinathan,et al. Negative feedback influence on simultaneous switching CMOS outputs , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.
[5] J. L. Prince,et al. Simultaneous switching ground noise calculation for packaged CMOS devices , 1991 .
[6] Cmos Outputs,et al. NEGATIVE FEEDBACK INFLUENCE ON SIMULTANEOUSLY SWITCHING , 1988 .
[7] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[8] Robert Michael Owens,et al. Modeling the effect of ground bounce on noise margin , 1994, Proceedings., International Test Conference.