A configurable high-throughput linear sorter system

Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel in order to increase throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Implementation of this system into a Field Programmable Gate Array (FPGA) results in a speedup of 68 compared to quicksort running in a MicroBlaze processor.

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