On-Chip Communication architecture

The present invention increases the utility of the ultimate communication architecture for transferring data between the on-chip circuitry, and offer the communication structure to eliminate waiting for the master to use the bus. And a direct memory access controller for a communication system according to the present invention are responsible for high-capacity data communication between the memory and the peripheral device, directly connected with the memory access controller, a header and containing information and continuous transmission length for the position of the passive circuit transmitted to the passive circuit the starting address from the active circuit, and a direct memory access controller and the communication switch to send and receive data, and a direct memory access controller and a memory controller to exchange data and address. According to the present invention, eliminates the active circuit request delay between the on-chip circuit, and can execute a data transfer number of active circuits at the same time, can also quickly and controls the communication congestion between them a large amount of data communication rate between the passive circuit is. Communication structure, a direct memory access controller (DMAC) between the on-chip circuit,