Emerging energy management techniques for chip multiprocessors

Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. While transistor technology continues to improve and become more energy efficient; it is clear that transistor technology alone will not completely address the power problem. Thus architectural solutions must also work to improve energy efficiency. This dissertation explores a range of energy management techniques to reduce energy consumption. Three techniques in particular are described. First, a quasi-static four transistor (4T) cell can be used to naturally decay large array structures which exhibit both spatial and temporal locality, such as the branch predictor, branch target buffer, and caches. 4T cells are smaller, consume less energy, and are approximately as fast as more traditional six-transistor (6T) cells. We show that 4T-based implementations for caches and branch predictors significantly reduces leakage energy yet impacts performance negligibly. Second, a novel coordinated dynamic voltage and frequency scaling (DVFS) policy guided by control-theoretic principles is described to reduce dynamic energy consumption of parallel applications on a chip multiprocessor. By extending a control-theoretic local DVFS control technique toward chip-multiprocessors, our technique prescribes DVFS settings formally at each tile, thus ensuring stable, distributed, coordinated DVFS control of a CMP. Last, a hardware-driven scheduler is introduced to improve both performance (in terms of throughput) and energy efficiency on CMPs. By adding hardware support to quickly select and place threads on a CMP, we not only improve run-time performance but also reduce the granularity of parallel program threads, further improving parallelism. With chip multiprocessors becoming more popular and energy consumption of major concern, techniques will be needed to improve energy efficiency. This work looks at some emerging energy consumption problems in chip multiprocessors and proposes several solutions to address these problems.