Energy-recovery CMOS for highly pipelined DSP designs

We compare the frequency-versus-power dissipation performance of two energy-recovery CMOS implementations to that of a conventional, supply-voltage-scaled design. The application is a small but complete DSP function. All three designs are based on the same high-level organization and conform to the same I/O specification. SPICE simulations indicate that an energy-recovery design which requires only a small degree of modification to the conventional design offers more than a two-fold reduction in power across a wide range of operating frequencies.

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