Circuit partitioning into small sets

Abstract We consider the problem of partitioning the elements of a circuit into sets that are allowed to have at most a constant number of elements so that the number of nets that connect elements in different sets is minimized. One application of the problem is in the design for testability and fault isolation of printed circuit boards. Other applications include rapid prototyping and circuit packaging. We present two heuristics for the problem that follow a bottom-up methodology which combines iterative improvement and graph matching techniques. The first heuristic has efficient performance. It is then modified to obtain an alternative heuristic with provably good performance. The time and space complexity of both heuristics is quadratic to the number of elements in the circuit. Both heuristics are superior to top-down partitioning approaches that use as subroutines existing circuit bipartitioning heuristics.

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