论文信息 - A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy

A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy

This paper presents the use of circuit simulations in understanding of the internal ESD (electrostatic discharge) failure observed in a 0.6 /spl mu/m CMOS technology product chip. Simulation of the ESD current paths near the V/sub dd/ pin are performed and the cause of ESD failure is identified using a circuit simulator that includes the MOS snapback models. These simulations are used to suggest issues to be considered in design of protection circuits to avoid this type of internal ESD failure.

C. Duvvury | V. Puvvada

[1] R. N. Rountree,et al. Internal chip ESD phenomena beyond the protection circuit , 1988 .

[2] C. Duvvury,et al. ESD: a pervasive reliability concern for IC technologies , 1993 .

[3] Anh Bui,et al. Unique ESD failure mechanisms during negative to Vcc HBM tests , 1998 .

[4] Amitava Chatterjee,et al. Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[5] S. Ramaswamy,et al. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations , 1996, Proceedings of International Reliability Physics Symposium.

[6] Scott Smith,et al. Unique ESD failure mechanisms during negative to WC 13bm tests , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[7] Charvaka Duvvury,et al. State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs , 1996 .