Leakage Power Reduction in CMOS VLSI

-With rapid changes in semiconductor technology chip density and frequency have increased, making the power consumption one of the major concern. Thus low power design has become the major challenge for present designers. Report says that 45% or even higher percentage of total power consumption is due to the leakage power of transistors. So reduction of leakage power is a great challenge for current and future technologies.in this paper, we are going to discuss different techniques for reducing the leakage power like dual threshold, transistor stacking, sleepy approach and variable threshold in CMOS VLSI circuit.