Adaptive supply serial links with sub-1 V operation and per-pin clock recovery

Adaptive power-supply regulation is extended to serial links, by using 5:1 multiplexing and low-voltage transceivers for power saving, and by scaling link properties with bit rate, especially in per-pin clock recovery PLL/DLLs. The serial link operates at 0.45-3.5 Gb/s for 0.9-2.5 V supply and dissipates 9.2-197 mW.

[1]  Mark Horowitz,et al.  Energy dissipation in general purpose microprocessors , 1996, IEEE J. Solid State Circuits.

[2]  M. Horowitz,et al.  An eight channel 35 GSample/s CMOS timing analyzer , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[3]  Michiel Steyaert,et al.  Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages , 1994, IEEE J. Solid State Circuits.

[4]  Gu-Yeon Wei,et al.  A fully digital, energy-efficient, adaptive power-supply regulator , 1999 .

[5]  M. Horowitz,et al.  A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver , 1999, IEEE Journal of Solid-State Circuits.

[6]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[7]  B. Razavi,et al.  A 2.75 Gb/s CMOS clock recovery circuit with broad capture range , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[8]  William J. Dally,et al.  Digital systems engineering , 1998 .

[9]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[10]  R. Jewett,et al.  Systems Engineering , 1959, IRE Transactions on Military Electronics.

[11]  M. Horowitz,et al.  Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[12]  T. Lee,et al.  A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter , 1999 .

[13]  Deog-Kyoon Jeong,et al.  A CMOS Serial Link for Fully Duplexed Data Communication(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .

[14]  Richard C. Walker,et al.  A two-chip 1.5-GBd serial link interface , 1992 .

[15]  M. Horowitz,et al.  Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[16]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[17]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[18]  Mark Horowitz,et al.  A 700-Mb/s/pin CMOS signaling interface using current integrating receivers , 1997 .

[19]  L. S. Nielsen,et al.  Low-power operation using self-timed circuits and adaptive scaling of the supply voltage , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997, IEEE J. Solid State Circuits.

[21]  Abraham Pressman,et al.  Switching Power Supply Design , 1997 .

[22]  Behzad Razavi Clock Recovery from Random Binary Signals , 1996 .

[23]  Anantha P. Chandrakasan,et al.  Techniques for aggressive supply voltage scaling and efficient regulation [CMOS digital circuits] , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[24]  Lin Wu,et al.  A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[25]  Eiji Takeda,et al.  An experimental 1.5-V 64-Mb DRAM , 1991 .

[26]  R. Gu,et al.  A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiver , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[27]  P. Schvan,et al.  A fully integrated SiGe receiver IC for 10-Gb/s data rate , 2000, IEEE Journal of Solid-State Circuits.

[28]  D. Finan,et al.  FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[29]  Anantha Chandrakasan,et al.  Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[30]  D. A. Fraser,et al.  The physics of semiconductor devices , 1986 .

[31]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[32]  J. Kim,et al.  An efficient digital sliding controller for adaptive power supply regulation , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[33]  P. Mattavelli,et al.  SLIDING MODE CONTROL OF DC-DC CONVERTERS , 2022 .

[34]  Kwyro Lee,et al.  A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme , 1997, IEEE J. Solid State Circuits.

[35]  M. Horowitz,et al.  A 700 Mbps/pin CMOS signalling interface using current integrating receivers , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[36]  M. Horowitz,et al.  A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation , 2000, IEEE Journal of Solid-State Circuits.

[37]  Lawrence T. Clark,et al.  15.1 A Scalable Performance 32b Microprocessor , 2001 .

[38]  Yiu-Fai Chan,et al.  A portable digital DLL for high-speed CMOS interface circuits , 1999, IEEE J. Solid State Circuits.

[39]  Jaeha Kim,et al.  An efficient digital sliding controller for adaptive power supply regulation , 2001, VLSIC 2001.

[40]  K. Donnelly,et al.  A 2.6 GB/s multi-purpose chip-to-chip interface , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[41]  Thomas H. Lee,et al.  A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM , 1994, IEEE J. Solid State Circuits.

[42]  M. G. Johnson,et al.  A Variable Delay Line Phase Locked Loop For Cpu-coprocessor Synchronization , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[43]  Thomas H. Lee,et al.  A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[44]  T. Lee,et al.  A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[45]  Marcel J. M. Pelgrom,et al.  Transistor matching in analog CMOS applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[46]  J. Lee,et al.  A 250 MHz low jitter adaptive bandwidth PLL , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[47]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[48]  P. Schvan,et al.  A fully integrated SiGe receiver IC for 10 Gb/s data rate , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[49]  P. C. Metz,et al.  A monolithic 50-200 MHz CMOS clock recovery and retiming circuit , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[50]  Chih-Kong Ken Yang,et al.  A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links , 1996 .

[51]  Yuyun Liao,et al.  A scalable performance 32 b microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[52]  M. Fukaishi,et al.  2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[53]  Juin J. Liou,et al.  SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests , 2001 .

[54]  W.J. Dally,et al.  Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.

[55]  Mike Galles Spider: a high-speed network interconnect , 1997, IEEE Micro.

[56]  M. Horowitz,et al.  - A 0 . 8pm CMOS 2 . 5 Gb / s Oversampling Receiver and Transmitter for Serial Links , 1999 .

[57]  M. Mitsuishi,et al.  A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand" , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[58]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[59]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[60]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[61]  Lizhong Sun,et al.  A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator , 2001, IEEE J. Solid State Circuits.