HIGH SPEED DIGITAL CMOS INPUT BUFFER DESIGN

Overview of the Project High speed digital Input buffer circuits are used in a wide variety of digital applications. One of the common applications of these input buffers is in memory devices. Memory circuits needs clean and full level digital data in the memory array. The digital data traveling through various digital circuitry gets distorted by adding delays in the signals like low voltage signal levels, slow rise and fall times, etc. The buffer circuits take these input signals with imperfections and convert them in to full digital logic levels by ‘slicing’ the data signals at correct levels which depends upon the switching point voltage. In this project, all the input buffer topologies employ self biased differential amplifiers because for buffers employing inverters in series, the switching point of the inverter varies due to the attenuation of the amplitude of the input signal. This project presents design, simulation, fabrication and characterization of novel, differential highspeed input buffers which mitigate all the above mentioned problems. The design of these input buffers has been processed in AMI’s CMOS processes with a die size of 1.5 x 1.5