Thermal-aware task scheduling for 3D-network-on-chip: A Bottom-to-Top scheme

3D-NoC emerges as a potential multi-core architecture delivering high performance, high energy efficiency and great scalability. However, severe thermal challenges due to high power density continue to be a major hurdle in the development of 3D-NoC. In this paper, we propose a novel thermal-aware task scheduling scheme named Bottom-to-Top (B2T) approach to address this challenge. Incorporating communication overhead into analysis based on task graph, this heuristic-based method judiciously performs task allocation on processing units to efficiently minimize the peak temperature and improve the execution time of the applications. Our simulation results demonstrate that our scheme can achieve significant peak temperature reduction (up to 7.95°C) and performance improvement (up to 4%) when compared to other methods.

[1]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[2]  Tajana Simunic,et al.  Temperature-aware MPSoC scheduling for reducing hot spots and gradients , 2008, 2008 Asia and South Pacific Design Automation Conference.

[3]  Margaret Martonosi,et al.  Techniques for Multicore Thermal Management: Classification and New Exploration , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[4]  Gabriel H. Loh,et al.  Thermal analysis of a 3D die-stacked high-performance microprocessor , 2006, GLSVLSI '06.

[5]  Edward G. Coffman,et al.  Computer and job-shop scheduling theory , 1976 .

[6]  Partha Pratim Pande,et al.  Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.

[7]  Karam S. Chatha,et al.  Approximation algorithm for the temperature-aware scheduling problem , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[8]  Mahmut T. Kandemir,et al.  Thermal-aware task allocation and scheduling for embedded systems , 2005, Design, Automation and Test in Europe.

[9]  Jun Yang,et al.  Thermal-Aware Task Scheduling for 3D Multicore Processors , 2010, IEEE Transactions on Parallel and Distributed Systems.

[10]  Mahmut T. Kandemir,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[11]  Akram Ben Ahmed,et al.  Low-overhead Routing Algorithm for 3D Network-on-Chip , 2012, 2012 Third International Conference on Networking and Computing.

[12]  2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014 , 2014, ISIC.

[13]  Li Shang,et al.  HybDTM: a coordinated hardware-software approach for dynamic thermal management , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[14]  Amit Kumar Singh,et al.  Thermal-aware mapping of streaming applications on 3D Multi-Processor Systems , 2013, The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia.

[15]  Tao Li,et al.  A Framework for Partitioning and Execution of Data Stream Applications in Mobile Cloud Computing , 2012, 2012 IEEE Fifth International Conference on Cloud Computing.

[16]  Jun Yang,et al.  Thermal Management for 3D Processors via Task Scheduling , 2008, 2008 37th International Conference on Parallel Processing.

[17]  Lei Jiang,et al.  Die Stacking (3D) Microarchitecture , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[18]  Marek Chrobak,et al.  Algorithms for Temperature-Aware Task Scheduling in Microprocessor Systems , 2008, AAIM.

[19]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[20]  Y.-K. Kwok,et al.  Static scheduling algorithms for allocating directed task graphs to multiprocessors , 1999, CSUR.

[21]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[22]  Kyriakos Stavrou,et al.  Thermal-Aware Scheduling for Future Chip Multiprocessors , 2007, EURASIP J. Embed. Syst..

[23]  Alioune Ngom,et al.  Genetic algorithm based scheduler for computational grids , 2005, 19th International Symposium on High Performance Computing Systems and Applications (HPCS'05).

[24]  Hironori Kasahara,et al.  A standard task graph set for fair evaluation of multiprocessor scheduling algorithms , 2002 .

[25]  Wei Zhang,et al.  A NoC Traffic Suite Based on Real Applications , 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

[26]  Alan J. Weger,et al.  Thermal-aware task scheduling at the system software level , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[27]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[28]  Yuzhuo Fu,et al.  Thermal management via task scheduling for 3D NoC based multi-processor , 2010, 2010 International SoC Design Conference.