Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures

Application-specific Systems-on-Chip (SoCs) introduce a set of various challenges for their interdisciplinary microelectronic implementation, from system theory (application) level over efficient CAD methods to suitable technologies, e. g. considering also reconfigurable hardware parts on different granularities. The paper sketches first major perspectives in architecture, design and application of Configurable Systems-on-Chip (CSoCs). The focus is the description of new CAD-algorithms for mapping automatized pre-synthesized IP-cores onto coarse-grain dynamically reconfigurable array architectures. Here, combinatorial optimization methods are combined with physical chip design algorithms, whereas dynamic reconfiguration of allocated hardware resources is considered.