Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this paper. Emphasis is placed on the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. The electroless Cu is used to make the seed layer, the laser direct imaging is used for opening the photoresist, and the printed circuit board Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the drop test and thermal cycling test are also performed.

[1]  Nicholas Kao,et al.  Warpage characterization of panel Fan-out (P-FO) package , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[2]  J. Bauer,et al.  From wafer level to panel level mold embedding , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[3]  John H. Lau,et al.  Fan-Out Wafer-Level Packaging , 2018 .

[4]  Naoki Hayashi,et al.  A novel Wafer level Fan-out Package (WFOP™) applicable to 50um pad pitch interconnects , 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

[5]  J. Bauer,et al.  24"×18" Fan-out panel level packing , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[6]  H. Hedler,et al.  An embedded device technology based on a molded reconfigured wafer , 2006, 56th Electronic Components and Technology Conference 2006.

[7]  J. Bauer,et al.  Large area compression molding for Fan-out Panel Level Packing , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[8]  John H. Lau.  Patent issues of embedded fan-out wafer/panel level packaging , 2016, 2016 China Semiconductor Technology International Conference (CSTIC).

[9]  Fumihiko Taniguchi,et al.  Advanced Embedded Packaging for Power Devices , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).

[10]  John H. Lau,et al.  Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs) , 2017 .

[11]  M. Brunnbauer,et al.  Embedded Wafer Level Ball Grid Array (eWLB) , 2008, 2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).

[12]  N. Lee,et al.  Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging , 2017, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[13]  Steve Chiu,et al.  Development and characterization of new generation panel fan-out (P-FO) packaging technology , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).