Time-division-multiplexing–wavelength- division-multiplexing-based architecture for ONoC

Future many-core processors will require high-performance yet energy-efficient on-chip networks to provide a communication substrate for the continually increasing number of cores on one chip. Optical networkon- chip (ONoC) is employed as a promising candidate interconnection solution for its high bandwidth and low energy consumption. However, optical circuit-switching (OCS) based architectures face the problem of high network congestion, low network utilization, and an overhead in power dissipation under heavy loads. In this paper, we propose an ONoC architecture with time-division multiplexing (TDM) and wavelength-division multiplexing (WDM) technology to solve the network contention problem faced by OCSbased ONoC. The number of wavelength groups and timeslots is optimized by using a genetic algorithm. A new optical router is designed to realize our TDM–WDM communication technology. A detailed model is built to analyze insertion loss and crosstalk noise. The simulation results show that TDM–WDM-based ONoC has better performance compared with equivalent OCS-mesh ONoC under a uniform traffic pattern. Similar analysis can be drawn for the real science application based on the PARSEC benchmark.

[1]  Huaxi Gu,et al.  Network condition-aware communication mechanism for circuit-switched optical networks-on-chips , 2016, IEEE/OSA Journal of Optical Communications and Networking.

[2]  K. Bergman,et al.  Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications , 2008, LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society.

[3]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[4]  M. Morse,et al.  31 GHz Ge n-i-p waveguide photodetectors on Silicon-on-Insulator substrate. , 2007, Optics express.

[5]  Keren Bergman,et al.  Optical interconnection networks for high-performance computing systems , 2012, Reports on progress in physics. Physical Society.

[6]  Ran Tao,et al.  Double image encryption based on random phase encoding in the fractional Fourier domain. , 2007, Optics express.

[7]  Wei Zhang,et al.  Crosstalk noise and bit error rate analysis for optical network-on-chip , 2010, Design Automation Conference.

[8]  Venkatesh Akella,et al.  Resilient microring resonator based photonic networks , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[9]  Yu Zhang,et al.  Firefly: illuminating future network-on-chip with nanophotonics , 2009, ISCA '09.

[10]  Ian O'Connor,et al.  Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology , 2011, 2011 Design, Automation & Test in Europe.

[11]  Abderazek Ben Abdallah,et al.  PHENIC: silicon photonic 3D-network-on-chip architecture for high-performance Heterogeneous many-core system-on-chip , 2013 .

[12]  Qianfan Xu,et al.  Silicon microring resonators with 1.5-μm radius , 2008 .

[13]  Alok Aggarwal,et al.  Efficient routing in optical networks , 1996, JACM.

[14]  Ian O'Connor,et al.  System level assessment of an optical NoC in an MPSoC platform , 2007 .

[15]  Christopher Batten,et al.  Silicon-photonic clos networks for global on-chip communication , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[16]  John Kim,et al.  FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[17]  George Kurian,et al.  ATAC: A 1000-core cache-coherent processor with on-chip optical network , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[18]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[19]  T.J.A. Popma,et al.  Bent asymmetric Y-branch integrated optical broadband wavelength multi/demultiplexer , 1994, IEEE Photonics Technology Letters.

[20]  Haibo Chen,et al.  IMR: High-Performance Low-Cost Multi-Ring NoCs , 2016, IEEE Transactions on Parallel and Distributed Systems.

[21]  Leonid Oliker,et al.  Silicon Nanophotonic Network-on-Chip Using TDM Arbitration , 2010, 2010 18th IEEE Symposium on High Performance Interconnects.

[22]  Randy Morris.  Energy-Efficient and High-Performance Nanophotonic Interconnects for Shared Memory Multicores , 2012 .

[23]  张磊,et al.  Economizing TSV Resources in 3-D Network-on-Chip Design , 2014 .

[24]  Ian O'Connor,et al.  Optical solutions for system-level interconnect , 2004, SLIP '04.

[25]  David H. Albonesi,et al.  Phastlane: a rapid transit optical routing network , 2009, ISCA '09.

[26]  Luca P. Carloni,et al.  Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  D.H. Albonesi,et al.  On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions , 2006, 2006 International Interconnect Technology Conference.

[28]  Huawei Li,et al.  ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Keren Bergman,et al.  Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors , 2011, JETC.

[30]  Yingtao Jiang,et al.  A Generic Optical Router Design for Photonic Network-on-Chips , 2012, Journal of Lightwave Technology.

[31]  Sailing He,et al.  A low-loss Y-branch with a multimode waveguide transition section , 2002, IEEE Photonics Technology Letters.

[32]  Qiaosha Zou,et al.  3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[33]  Weihua Xu,et al.  Performance Optimization and Evaluation for Torus-Based Optical Networks-on-Chip , 2015, Journal of Lightwave Technology.

[34]  Jung Ho Ahn,et al.  Devices and architectures for photonic chip-scale integration , 2009 .

[35]  John E. Bowers,et al.  8 × 8 × 40 Gbps fully integrated silicon photonic network on chip , 2016 .

[36]  P. Dumon,et al.  Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides. , 2007, Optics letters.