Top Gate Tft for Large Area Electronics

The TFT fabrication by PECVD at low processing temperature ( −12 A, the threshold voltage of 15V and the field effect mobility of 10 −2 cm 2 /(Vs). To increase the field-effect mobility, reduce the threshold voltage, and reduce the mask count, nanocrystalline silicon based top gate TFT was designed. The TFT fabrication process was done at maximum processing temperature of 75°C. The direct PECVD SiN x and SiO x /SiN x stack were used as gate dielectrics. Nanocrystalline silicon was used as the channel layer. The SiN x gate dielectric TFTs demonstrated the leakage current about 10 −13 A, the threshold voltage of 8..10V, the field effect mobility of ∼10 −4 cm 2 /(Vs), the subthreshold slope of 4..8V/decade, and I on /I off ratio of about 10 2 . High source and drain contact resistance were attributed to low efficiency of phosphorous doping in amorphous silicon at 75°C, which also limited the I on value. Using n + nc-Si for the source and drain contacts, the I on /I off ratio was increased to 10 6 , and the field effect mobility was increased to ∼0.1cm 2 /(Vs). The threshold voltage, however, increased, which was attributed to higher fixed charge.