A study of pipelined pseudo-exhaustive testing on VLSI circuits with feedback

An extensive empirical study on feedback paths in pipelined pseudo-exhaustive testing (PPET) is conducted. Feedback paths have impact on testing time for achieving certain fault coverage. Aliasing probability of looped PPET stays in O(2/sup -N/) when N-bit CBITs are used as signature analyzer for test length longer than 2/sup N/ clock cycles. The overall testing time is then dominated by O(2/sup N/) clock cycles for PPET. Our study proves PPET is an efficient solution for testing complex circuits and systems.<<ETX>>

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