FinFET With High- $\kappa $ Spacers for Improved Drive Current

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO<sub>2</sub> high-κ spacer and compare it with its counterpart having SiO<sub>2</sub> low-κ spacer. The HfO<sub>2</sub> spacer structure reduces series resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO<sub>2</sub> spacer device by about 3× when biased in the saturation region, and about 1.6× and 2×, respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO<sub>2</sub> spacer.

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