Completion detection in dual-rail asynchronous systems by current-sensing

Abstract In this article, we address a novel methodology of detecting a computation completion of the combinatorial block in asynchronous digital systems. The proposed methodology is based on well-known phenomenon that occurs in digital systems realized in CMOS technology. CMOS logic circuits exhibit significantly higher current consumption during the signal transitions than in the static state. This effect can be exploited to separate the idle state from the computation process. The paper presents fundamental background of the completion detection methodology, detailed description of developed current sensor circuitry, achieved simulation results as well as the comparison with the state-of-the-art methods of completion detection and previous research that has been done in this scientific area.

[1]  Stephen B. Furber,et al.  Built-in self-testing of micropipelines , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[2]  C. Andre T. Salama,et al.  Low-power asynchronous Viterbi decoder for wireless applications , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[3]  Rob A. Rutenbar,et al.  Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS , 2008, Proceedings of the IEEE.

[4]  Kiyoshi Oguri,et al.  Asynchronous Circuit Design , 2001 .

[5]  Chang-Jiu Chen,et al.  A pipelined asynchronous 8051 soft-core implemented with Balsa , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[6]  I. I. Shagurin,et al.  Physical approach to CMOS module self-timing , 1990 .

[7]  Phillip E. Allen,et al.  A low-voltage, bulk-driven MOSFET current mirror for CMOS technology , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[8]  Olli Vainio,et al.  Current-sensing completion detection method for standard cell based digital system design , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[9]  Olli Vainio,et al.  Dynamically biased current sensor for current-sensing completion detection , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[10]  H. Lampinen,et al.  Circuit design for current-sensing completion detection , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[11]  Izzet Kale,et al.  Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timing , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[12]  H. Lampinen,et al.  Implementation of a self-timed asynchronous parallel FIR filter using CSCD , 2004, Proceedings Norchip Conference, 2004..

[13]  Fu-Chiung Cheng.  Practical design and performance evaluation of completion detection circuits , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[14]  M. Hevery.  Asynchronous circuit completion detection by current sensing , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[15]  Olli Vainio,et al.  Design of a self-timed asynchronous parallel FIR filter using CSCD , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[16]  P. Dinesh Kumar,et al.  Design of Delay Based Dual Rail Precharge Logic to reduce DPA attacks , 2012, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET).

[17]  Mark Horowitz,et al.  Self-timed logic using current-sensing completion detection (CSCD) , 1991 .

[18]  M. Santhi,et al.  Transient current sensing based completion detection with event separation logic for high speed asynchronous pipelines , 2009, TENCON 2009 - 2009 IEEE Region 10 Conference.

[19]  Alain J. Martin,et al.  Asynchronous Pulse Logic , 2002 .

[20]  Luciano Lavagno,et al.  Methodology and tools for state encoding in asynchronous circuit synthesis , 1996, DAC '96.

[21]  V. I. Varshavsky,et al.  Critical view on the current sensor application for self-timing in VLSI systems , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[22]  Yousaf Zafar,et al.  Design of asynchronous MSP430 microprocessor using balsa back-end retargeting , 2009, 2009 5th Southern Conference on Programmable Logic (SPL).

[23]  Hardeep Singh.  Power Aware Design and Implementation of 8-bit Asynchronous Arithmetic and Logic Unit , 2009, 2009 IEEE International Advance Computing Conference.

[24]  Viera Stopjakova,et al.  Current sensing methodology for completion detection in self-timed systems , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[25]  Eckhard Grass,et al.  Asynchronous circuits based on multiple localised current-sensing completion detection , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[26]  Feng Shi,et al.  A transistor-level test strategy for C/sup 2/MOS MOUSETRAP asynchronous pipelines , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[27]  Christos P. Sotiriou.  Implementing asynchronous circuits using a conventional EDA tool-flow , 2002, DAC '02.

[28]  Atsushi Kurokawa,et al.  Challenge: variability characterization and modeling for 65- to 90-nm processes , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..