A Fast and Power–Area-Efficient Accumulator for Flying-Adder Frequency Synthesizer

The flying-adder frequency synthesis architecture is a novel approach of generating frequencies on chip. Since its invention, it has been used in many commercial products to cope with difficult frequency generation challenges. Along the course of this architecture's evolution, various circuit- and system-level problems have been resolved. In this paper, one remaining problem related to circuit implementation, namely, the construction of the accumulator, is studied. A new scheme is proposed to achieve the flying-adder accumulation function that not only has speed advantage but also is power and area efficient. The issue related to time-average frequency and jitter is also discussed.

[1]  Xiaohong Jiang,et al.  Statistical skew modeling for general clock distribution networks in presence of process variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  S. Naffziger,et al.  Statistical clock skew modeling with data delay variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[3]  J. Meiners,et al.  A novel all-digital PLL with software adaptive filter , 2004, IEEE Journal of Solid-State Circuits.

[4]  Yingtao Jiang,et al.  Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates , 2002 .

[5]  Mary Jane Irwin,et al.  Area-time-power tradeoffs in parallel adders , 1996 .

[6]  Liming Xiu,et al.  A "Flying-Adder" frequency synthesis architecture of reducing VCO stages , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Liming Xiu,et al.  An architecture of high-performance frequency and phase synthesis , 2000, IEEE Journal of Solid-State Circuits.

[8]  Massimo Alioto,et al.  Analysis and comparison on full adder block in submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Yin-Tsung Hwang,et al.  A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Bosco H. Leung,et al.  A novel model on phase noise of ring oscillator based on last passage time , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Liming Xiu,et al.  A new frequency synthesis method based on "flying-adder" architecture , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[12]  Liming Xiu.  A Novel DCXO Module for Clock Synchronization in MPEG2 Transport System , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Liming Xiu.  A “Flying-Adder” On-Chip Frequency Generator for Complex SoC Environment , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Bosco H. Leung,et al.  Investigation of phase noise of ring oscillators with time-varying current and noise sources by time-scaling thermal noise , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Liming Xiu.  The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture , 2008, IEEE Circuits and Systems Magazine.

[16]  Beomsup Kim,et al.  Analysis of timing jitter in CMOS ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[17]  Liming Xiu.  A Flying-Adder PLL technique enabling novel approaches for video/graphic applications , 2008, IEEE Transactions on Consumer Electronics.

[18]  A. Demir,et al.  Phase noise and timing jitter in oscillators , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[19]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Liming Xiu,et al.  A "flying-adder" architecture of frequency and phase synthesis with scalability , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[21]  Liming Xiu.  Some open issues associated with the new type of component: digital-to-frequency converter [Open Column] , 2008, IEEE Circuits and Systems Magazine.

[22]  Magdy A. Bayoumi,et al.  Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Mark Horowitz,et al.  Timing analysis including clock skew , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Liming Xiu,et al.  "Flying-Adder" PLL Based Synchronization Mechanism for Data Packet Transport , 2007, 2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip.

[25]  Venceslav F. Kroupa,et al.  Jitter and phase noise in frequency dividers , 2001, IEEE Trans. Instrum. Meas..

[26]  A.A. Abidi,et al.  Phase Noise and Jitter in CMOS Ring Oscillators , 2006, IEEE Journal of Solid-State Circuits.