Soft Error Performance of Z-RAM Floating Body Memory
暂无分享,去创建一个
The zero-capacitor (Z-RAMreg) floating body memory is a dynamic memory built on an SOI substrate. It differs from a DRAM cell in that it does not rely on an external capacitor to store charge and reading is done by sensing cell current. The Z-RAM memory cell stores charge in its floating body and uses this charge to alter the threshold voltage and gain of the cell transistor. The advantages of the Z-RAM cell are numerous and include a smaller cell size, lithographic friendly processing, fast access time, and no additional processing steps for use as an embedded memory (Okhonin et al., 2001). However, there is little published data on the soft error rates (SER) of this type of memory. This paper summarizes the results of accelerated alpha particle testing conducted on four, 1 Mbit Z-RAM test vehicles. As expected from the nature of the Z-RAM operation and its small cell size, its SER was observed to be significantly better than SRAM and comparable to the SER performance of embedded DRAM
[1] R. Baumann. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction , 2002, Digest. International Electron Devices Meeting,.
[2] Changhong Dai,et al. Impact of CMOS process scaling and SOI on the soft error rates of logic processes , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
[3] Yoshiharu Tosaka,et al. Alpha-particle-induced collected charge model in SOI-DRAM's , 1999 .