Hardware Acceleration of Nonlocal Means-Based Speckle Noise Removal Applied to SAR Imagery

Removal of speckle noise from synthetic aperture radar (SAR) remains a challenging obstacle for onboard processing. Speckle noise is substantially harder to address than Gaussian noise due to its multiplicative nature. The probability patch-based (PPB) filter is based on the nonlocal means filter and can reduce speckle noise while preserving fine details. However, its high computational complexity inhibits its practical use in embedded applications. This is especially true for conventional space platforms, where radiation-hardened processors have significantly lower performance and energy-efficiency than their commercial-off-the-shelf counterparts. Combined with ever-increasing demands for data processing requirements and an emphasis on intelligent, autonomous systems, there is a need to enhance computing capabilities of space platforms for present and future missions. Recently, use of hybrid system-on-chip (SoC) devices in space applications has been increasingly adopted. Namely, CPU+FPGA devices present several opportunities for efficient acceleration of many applications in comparison to software-only architectures. In this paper, a detailed description of a CPU+FPGA accelerator for speckle noise removal implementing the PPB filter is presented. The proposed architecture leverages the strengths of CPUs and FPGAs to maximize performance. Studying the dataflow and computation properties of the algorithm allow for a highly parallelized and fully pipelined design. When evaluated on the Xilinx Z-7045 SoC, our proposed architecture shows a significant execution time improvement (up to ~750x) over a software-only baseline while maintaining modest FPGA resource utilization. To verify its function, filtering quality is evaluated using images artificially corrupted by simulated speckle noise as well as real SAR images. Quantitative analysis shows that use of the hardware design only introduces negligible quality loss.