Combinational logic SER estimation with the presence of re-convergence

As transistor feature size scales down, re-convergence takes more and more significant effect to SER (Soft error rate) estimation in combinational logic. In this paper, we propose 4 forms of re-convergence in 2-input logic gates, ROR, RSUB, RAND and RXOR, and for each form the sensitization condition is presented. The results are extended to more complex gates. Based on our re-convergence analysis technique, we implement a SER analyze framework of combinational logic with re-convergence, SERAR (Soft Error Rate Analyze with Re-convergence). Experiments on ISCAS'85 benchmark circuit show that re-convergence introduces average 12% ~ 41% error in SER estimation for each gate.

[1]  Diana Marculescu,et al.  MARS-C: modeling and reduction of soft errors in combinational circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[2]  Yuan Xie,et al.  Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model , 2011, IEEE Transactions on Dependable and Secure Computing.

[3]  Sujit Dey,et al.  A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits , 2004, Proceedings. 41st Design Automation Conference, 2004..

[4]  Mehdi Baradaran Tahoori,et al.  An accurate SER estimation method based on propagation probability [soft error rate] , 2005, Design, Automation and Test in Europe.

[5]  Diana Marculescu,et al.  Soft error rate analysis for sequential circuits , 2007 .

[6]  G. R. Srinivasan,et al.  Soft-error Monte Carlo modeling program, SEMM , 1996, IBM J. Res. Dev..

[7]  C. Metra,et al.  A model for transient fault propagation in combinatorial logic , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[8]  Gerald M. Masson,et al.  The Boolean Difference and Multiple Fault Analysis , 1975, IEEE Transactions on Computers.

[9]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[10]  P. Eaton,et al.  Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes , 2005, IEEE Transactions on Nuclear Science.

[11]  Diana Marculescu,et al.  MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[12]  Elizabeth M. Rudnick,et al.  A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults , 1996, IEEE Trans. Computers.

[13]  Ming Zhang,et al.  A soft error rate analysis (SERA) methodology , 2004, ICCAD 2004.

[14]  Bin Zhang,et al.  FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[15]  Nur A. Touba,et al.  Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[16]  Diana Marculescu,et al.  Circuit Reliability Analysis Using Symbolic Techniques , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.