Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS

This paper presents an analysis on energy dissipation of designs when operated in sub-threshold (sub-VT) regime. Four reference architectures are used to investigate the impact of switching activity μe on energy and energy minimum voltage (EMV). The designs are synthesized in a 65 nm low-leakage CMOS technology with high-threshold voltages cells. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The simulation results show that with low μe the EMV of a design moves closer to the threshold voltage and visa versa, up to a change of 104mV for the observed architectures. Furthermore a loss in frequency by one order of magnitude is observed. It is also observed that for these architectures operation at a sub-optimal frequency leads to loss in energy dissipation. However, by correct selection of operational clock frequency the energy dissipation is reduced by order of magnitudes.