Compact Modeling of Variation in FinFET SRAM Cells

FinFET technology is a possible solution to achieve a better power/performance trade-off for SRAM cells. This article provides a comprehensive analysis of the variations in FinFET devices, their impact on SRAM stability, and a statistical design procedure for FinFET SRAM cells.

[1]  Zheng Guo,et al.  Large-scale read/write margin measurement in 45nm CMOS SRAM arrays , 2008, 2008 IEEE Symposium on VLSI Circuits.

[2]  C. Hu,et al.  Threshold voltage model for deep-submicrometer MOSFETs , 1993 .

[3]  C. Hu,et al.  BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design , 2007, 2007 IEEE Symposium on VLSI Technology.

[4]  W. Haensch,et al.  Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond , 2008, 2008 IEEE International Electron Devices Meeting.

[5]  Chenming Hu,et al.  Performance-Aware Corner Model for Design for Manufacturing , 2009, IEEE Transactions on Electron Devices.

[6]  Ali M. Niknejad,et al.  Design of FinFET SRAM Cells Using a Statistical Compact Model , 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

[7]  Hiroyuki Yamauchi A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era , 2009 .

[8]  R. Rooyackers,et al.  A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM , 2007, 2007 IEEE Symposium on VLSI Technology.

[9]  Yuhua Cheng,et al.  MOSFET Modeling and Bsim3 User's Guide , 1999 .

[10]  Zheng Guo,et al.  FinFET-based SRAM design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[11]  Chenming Hu,et al.  Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[12]  Chung-Hsun Lin,et al.  Compact Modeling of Nanoscale CMOS , 2007 .