Study of bending-induced strain effects on MuGFET performance
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C.R. Cleavelin | P. Patruno | T. Schulz | K. Schruefer | Weize Xiong | W. Xiong | L. Smith | T. Schulz | K. Schruefer | Tsu-Jae King Liu | C. Cleavelin | P. Patruno | K. Shin | Chung Yeung Cho | L. Smith | K. Shin | C. Y. Cho
[1] Jeffrey Bokor,et al. Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.
[2] A. Chou,et al. High performance CMOS fabricated on hybrid substrate with different crystal orientations , 2003, IEEE International Electron Devices Meeting 2003.
[3] T. Liu,et al. FinFET Performance Enhancement with Tensile Metal Gates and Strained Silicon on Insulator (sSOI) Substrate , 2006, 2006 64th Device Research Conference.
[4] T. Lauderdale,et al. Effect of tensile capping layer on 3-D stress profiles in FinFET channels , 2005, 63rd Device Research Conference Digest, 2005. DRC '05..
[5] C. Mazure,et al. Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility , 2006, IEEE Electron Device Letters.
[6] E. Sleeckx,et al. Performance improvement of tall triple gate devices with strained SiN layers , 2005, IEEE Electron Device Letters.
[7] Charles S. Smith. Piezoresistance Effect in Germanium and Silicon , 1954 .
[8] M. Bohr,et al. A logic nanotechnology featuring strained-silicon , 2004, IEEE Electron Device Letters.
[9] Y. Nishi,et al. Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[10] R. Rooyackers,et al. A systematic study of trade-offs in engineering a locally strained pMOSFET , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[11] R. Rooyackers,et al. 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
[12] Chenming Hu,et al. Sub-60-nm quasi-planar FinFETs fabricated using a simplified process , 2001, IEEE Electron Device Letters.
[13] M. Silberstein,et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors , 2003, IEEE International Electron Devices Meeting 2003.
[14] D. Hisamoto,et al. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.
[15] D. Hisamoto,et al. A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET , 1990, IEEE Electron Device Letters.