Design and implementation of a two-dimensional fast Fourier transform chip

The authors describe a rasterized pipelined architecture for performing a two-dimensional fast Fourier transformation (2DFFT). Incorporating over 152,000 transistors in 1.25 mu m CMOS on a 9 mu m die, the chip functions at a clock speed of 10 MHz, processing a 256*256-pixel image at a real-time frame rate of 30 Hz. The input and output data formats are rasterized streams of 22-bit fixed-point complex numbers. The authors present the chip architecture and describe the design of its constituent units. On-chip storage of the sine/cosine factors and the absence of a corner-turning memory are this design's most novel features.<<ETX>>