Multi-gigahertz low-power low-skew rotary clock scheme

On-chip clock frequencies in the gigaHertz range require generators with low skew and low jitter to avoid timing problems. This rotary clock distribution architecture provides low-skew low-jitter, gigaHertz-rate clocking with high edge rates and low power consumption, works over a wide power supply range and is completely scalable. The frequency is limited only by f/sub T/ of the integrated circuit technology used; an f/sub T/ of approximately 30 GHz produces square waves with 20 ps transition times. In addition, there is no limit to the size of the chip that can be clocked, and both multiphase and non-overlapping noise-immune differential clocking are supported.

[1]  B. Kleveland,et al.  Monolithic CMOS distributed amplifier and oscillator , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  Vernon L. Chi Salphasic Distribution of Clock Signals for Synchronous Systems , 1994, IEEE Trans. Computers.

[3]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.