Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

An efficient solution to the wire sizing problem using the Elmore delay model is proposed. Two formulations of the problem are put forth. In the first, the minimum interconnect delay is sought, while in the latter, we minimize the net delay under delay constraints at the leaf nodes; previous approaches solve only the former problem. Theoretical results on these problems are proved, and two algorithms are presented. One is a sensitivity-based heuristic, while the other is a rigorous convex optimization problem. It is shown experimentally that the sensitivity-based heuristic gives near-optimal results with reasonable runtimes. A smooth area-delay tradeoff is shown, and results are presented to illustrate the fact that sizing for minimum delay is not a good engineering goal. Instead, a delay goal of even 15% over the minimum provides significantly better engineering solutions.

[1]  Sung-Mo Kang,et al.  An exact solution to the transistor sizing problem for CMOS circuits using convex optimization , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  J. Ecker Geometric Programming: Methods, Computations and Applications , 1980 .

[3]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Pravin M. Vaidya,et al.  A new algorithm for minimizing convex functions over convex sets , 1989, 30th Annual Symposium on Foundations of Computer Science.

[5]  A.L. Sangiovanni-Vincentelli,et al.  A survey of optimization techniques for integrated-circuit design , 1981, Proceedings of the IEEE.

[6]  Sachin S. Sapatnekar,et al.  A convex optimization approach to transistor sizing for CMOS circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[7]  Pravin M. Vaidya,et al.  A new algorithm for minimizing convex functions over convex sets , 1996, Math. Program..

[8]  Jason Cong,et al.  Optimal wiresizing under Elmore delay model , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Paul Penfield,et al.  Signal Delay in RC Tree Networks , 1981, 18th Design Automation Conference.