Carbon nanotube bundles as nanoscale chip to package interconnects

The paper presents recent advances in carbon nanotube interconnect modeling, with focus on their application to nanoscale chip packaging. An enhanced electrical model of carbon nanotube bundles is used, able to take into account the effects of different nanotube sizes covered by this application. The use of carbon nanotubes as chip to package interconnects at nanoscale dimensions is analyzed and the electrical parasitics introduced by these interconnects are compared to those predicted by other packaging technologies.

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