Plug and play chip testing vector generating circuit and method

The invention relates to large-scale integrated circuit technology field, especially relates to plug-and-play on-chip test vector generated circuit and method. The method and the circuit core are a non-invaded on-chip test vector generating circuit. The test vector generating circuit includes two primary parts and freezing control circuit, the two primary parts are: 1) decode. The decoder generates selecting and mending signal to amend the value in the feedback shift register according to the content loaded by the test slave device, thus the linear feedback shift register can generate the expected test vector. 2) Single value controllable linear feedback shift register. It is used to amend the seed, generates the test vector automatically. The freezing control circuit provides vector automatic generating mechanism of multi-value amendment and length variable window, thus the test vector generating process has flexibility. Because that the test vector generating circuit can generate determined test vector, it guarantees the failure covering rate.