Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool

This paper describes how a commercial tool for design of digital signal processing systems at the algorithmic level has been adapted to generate VHDL that can serve as input for simulation and synthesis. Special attention will be paid to how the VHDL has to be generated in order to allow efficient synthesis using a popular commercial tool. At the same time the VHDL must be flexible so that it can provide input to other synthesis tools in the future, and generic enough to simulate on any commercial VHDL-simulator.