Design and Simulation of Low-power Conditional-Discharging Flip Flop

In this seminal, a low-power conditional discharging-flip flop (Modified CD-FF) has been presented. A clock-pulse by single feedback through scheme is proposed for use in the Modified CD-FF. Two inverters in clock-pulse generator circuit have been removed to optimize delay in clock path. In this low-power circuit design, the clock pulse is designed by a single inverter and pass-transistor logic (PTL). The proposed circuit (MCD-FF) reduces the additional switching activity of certain internal nodes as well as generates less glitch in the output with a lesser transistor count. As a consequence, the width of transistor is increased to manage the delay for clock pulse. Overall performances of circuit design provides better optimized area, delay and power consumption (average power) than earlier flip flop designs compared to 90nm technology.

[1]  Massimo Alioto,et al.  General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Yin-Tsung Hwang,et al.  Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Young-Hyun Jun,et al.  Conditional-capture flip-flop for statistical power reduction , 2001, IEEE J. Solid State Circuits.

[4]  Vojin G. Oklobdzija,et al.  Conditional techniques for low power consumption flip-flops , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[5]  F. Klass.  Semi-dynamic and dynamic flip-flops with embedded logic , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[6]  Massimo Alioto,et al.  Analysis and Comparison in the Energy-Delay-Area Domain , 2015 .

[7]  Massimo Alioto,et al.  Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Uming Ko,et al.  High-performance energy-efficient D-flip-flop circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Peiyi Zhao,et al.  Low power and high speed explicit-pulsed flip-flops , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[10]  N. Nedovic,et al.  Hybrid latch flip-flop with improved power efficiency , 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).

[11]  James Tschanz,et al.  Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.

[12]  Huazhong Yang,et al.  Low clock-swing conditional-precharge flip-flop for more than 30% power reduction , 2000 .

[13]  F. Weber,et al.  Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[14]  Vladimir Stojanovic,et al.  Digital System Clocking: High-Performance and Low-Power Aspects , 2003 .

[15]  Kiat Seng Yeo,et al.  A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[16]  Manoj Sachdev,et al.  A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[17]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[18]  Tarek Darwish,et al.  High-performance and low-power conditional discharge flip-flop , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Hiroshi Kawaguchi,et al.  A reduced clock-swing flip-flop (RCSFF) for 63% power reduction , 1998, IEEE J. Solid State Circuits.

[20]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[21]  Vojin G. Oklobdzija,et al.  Conditional pre-charge techniques for power-efficient dual-edge clocking , 2002, ISLPED '02.

[22]  Zhongfeng Wang,et al.  Design of Sequential Elements for Low Power Clocking System , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.