Sporadic Charging In Interlevel Oxide Deposition In Conventional Plasma And HDP Deposition Systems

Charging damage at interlevel dielectric deposition has been investigated for CMOS technologies with gate-oxide thickness of 7.0-7.8 nm. The charging damage is revealed in NFETs and PFETs by hot electron stressing. This charging is not consistent from wafer to wafer or job to job, but is sporadic. It is also observed to be very dependent on the specific tool used for the process. By increasing the pressure in the TEOS-based intermetal dielectric (IMD) deposition process, the rate of affected wafers in the worst tools is reduced from 30% to essentially zero. A high-density plasma deposition (HDPCVD) is also shown to be virtually damage-free for a technology with gate oxide of 5.0 nm.

[1]  V. McGahay,et al.  Process-Induced Gate Oxide Damage Issues in Advanced Plasma Chemical Vapor Deposition Processes , 1996, Proceedings of 1st International Symposium on Plasma Process-Induced Damage.

[2]  Terence B. Hook,et al.  A Comparison Of Hot-electron And Fowler-nordheim Characterization Of Charging Events In A 0.5-/spl mu/m Cmos Technology , 1996, Proceedings of 1st International Symposium on Plasma Process-Induced Damage.

[3]  E. Nowak,et al.  A CMOS Technology for a Sub-5-ns 3.3-V LVTTL 1-Mbit SRAM , 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

[4]  A. Stamper,et al.  Plasma‐induced gate‐oxide charging issues for sub‐0.5 μm complementary metal–oxide–semiconductor technologies , 1995 .

[5]  A. Kordesch,et al.  Plasma Damages of Thin Oxide Measured by a Large Charge Collecting Antenna Structure , 1995 .

[6]  J. McVittie,et al.  Real time measurement of transients and electrode edge effects for plasma charging induced damage , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[7]  Y. Chan.  Using SEMATECH electrical test structures in assessing plasma induced damage in poly etching , 1994 .

[8]  W. Lukaszek,et al.  Characterization of wafer charging mechanisms and oxide survival prediction methodology , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[9]  M.-R. Lin,et al.  Characterization and optimization of metal etch processes to minimize charging damage to submicron transistor gate oxide , 1994, IEEE Electron Device Letters.

[10]  Koichi Hashimoto,et al.  New Phenomena of Charge Damage in Plasma Etching: Heavy Damage Only through Dense-Line Antenna , 1993 .

[11]  J. McVittie,et al.  Charging damage to gate oxides in an O2 magnetron plasma , 1992 .

[12]  C. K. Lau,et al.  Process‐Induced Gate Oxide Charge Collector Damage , 1992 .

[13]  R. R. Uttecht,et al.  A four-level-metal fully planarized interconnect technology for dense high performance logic and SRAM applications , 1991, 1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.