Chip Level Modeling With Vhdl

VLSI circuits have made gate-level modeling of large-scale systems impractical. Chip-level modeling offers an alternative approach to model development that still represents timing accurately. The authors examine this approach to modeling and the use of hardware description languages (HDLs) to achieve the desired accuracy. The characteristics of chip-level models are reviewed and sample models are presented. HDL code for each model is given to illustrate its use. Fault modeling in a chip level is examined. >

[1]  James R. Armstrong,et al.  Simulation techniques for microprocessors , 1977, DAC '77.

[2]  Tom Blank,et al.  A Survey of Hardware Accelerators Used in Computer-Aided Design , 1984, IEEE Design & Test of Computers.

[3]  Special Feature Chip-Level Simulation of Microprocessors , 1980, Computer.

[4]  James R. Armstrong.  Chip Level Modeling of LSI Devices , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  T.M. McWilliams.  Verification of Timing Constraints on Large Digital Systems , 1980, 17th Design Automation Conference.

[6]  James R. Armstrong,et al.  GSP: A Logic Simulator for LSI , 1981, 18th Design Automation Conference.

[7]  James R. Armstrong,et al.  Functional Fault Modeling and Simulation for VLSI Devices , 1985, DAC 1985.

[8]  James R. Armstrong,et al.  A Heuristic Chip-Level Test Generation Algorithm , 1986, DAC 1986.

[9]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[10]  Frederick J. Hill,et al.  Introduction to Switching Theory and Logical Design , 1968 .

[11]  James R. Armstrong.  Chip level modeling and simulation , 1983 .