FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT

This paper presents a novel architecture for the enhancement of performance of compute intensive Fast Fourier Transform (FFT) algorithm which is common in many signal processing applications. The proposed architecture exhibits faster response time compared to radix-2 'Single-path Delay Feedback (SDF)' architecture and 'radix-2 Multi-path Delay Commutator (MDC)' architecture. The architecture was simulated using Modelsim and was implemented on Xilinx Virtex 4 FPGA.

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