Lightweight Software-Defined Error Correction for Memories

[1]  Rakesh Kumar,et al.  Correction prediction: Reducing error correction latency for on-chip memories , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[2]  Lara Dolecek,et al.  Low-Cost Memory Fault Tolerance for IoT Devices , 2017, ACM Trans. Embed. Comput. Syst..

[3]  Lara Dolecek,et al.  Parity++: Lightweight Error Correction for Last Level Caches , 2018, 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W).

[4]  Onur Mutlu,et al.  Mitigating the Memory Bottleneck With Approximate Load Value Prediction , 2016, IEEE Design & Test.

[5]  Eiji Fujiwara,et al.  Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems , 1982, IEEE Transactions on Computers.

[6]  Mikko H. Lipasti,et al.  Value locality and load value prediction , 1996, ASPLOS VII.

[7]  Mario Badr,et al.  Load Value Approximation , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[8]  Song Liu,et al.  Flikker: saving DRAM refresh-power through critical data partitioning , 2011, ASPLOS XVI.

[9]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[10]  Jun Yang,et al.  Frequent value compression in data caches , 2000, MICRO 33.

[11]  Hadi Esmaeilzadeh,et al.  AxBench: A Multiplatform Benchmark Suite for Approximate Computing , 2017, IEEE Design & Test.

[12]  Puneet Gupta,et al.  VaMV: Variability-aware Memory Virtualization , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Gedare Bloom,et al.  SuperGlue: IDL-Based, System-Level Fault Tolerance for Embedded Systems , 2016, 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

[14]  Onur Mutlu,et al.  Linearly compressed pages: A low-complexity, low-latency main memory compression framework , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[15]  Jeffrey S. Vetter,et al.  A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems , 2016 .

[16]  Dan Grossman,et al.  EnerJ: approximate data types for safe and general low-power computation , 2011, PLDI '11.

[17]  Frederic Sala,et al.  Context-aware resiliency: Unequal message protection for random-access memories , 2017, 2017 IEEE Information Theory Workshop (ITW).

[18]  Lara Dolecek,et al.  Software-Defined ECC: Heuristic Recovery from Uncorrectable Memory Errors - eScholarship , 2017 .

[19]  Mattan Erez,et al.  Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[20]  Puneet Gupta,et al.  ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings , 2015, IEEE Transactions on Computers.

[21]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[22]  Lara Dolecek,et al.  Software-Defined Error-Correcting Codes , 2016, 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W).

[23]  Natalie D. Enright Jerger,et al.  The Bunker Cache for spatio-value approximation , 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[24]  Nikil D. Dutt,et al.  E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories , 2011, 2011 Design, Automation & Test in Europe.

[25]  Alexander A. Davydov,et al.  An alternative to the Hamming code in the class of SEC-DED codes in semiconductor memory , 1991, IEEE Trans. Inf. Theory.

[26]  Onur Mutlu,et al.  Base-delta-immediate compression: Practical data compression for on-chip caches , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

[27]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[28]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[29]  David A. Wood,et al.  Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches , 2004 .

[30]  Andrew Waterman,et al.  The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 , 2014 .