Digital Acceleration of Correlation-Based Digital Background Calibration in Pipelined ADCs
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[1] Kyoungho Woo,et al. Fast-Lock Hybrid PLL Combining Fractional- $N$ and Integer-$N$ Modes of Differing Bandwidths , 2008, IEEE Journal of Solid-State Circuits.
[2] Ian Galton. Digital cancellation of D/A converter noise in pipelined A/D converters , 2000 .
[3] M. Sawan,et al. Background capacitor mismatch calibration for pipelined ADC , 2003, 2003 46th Midwest Symposium on Circuits and Systems.
[4] Ian Galton,et al. Digital Background Correction of Harmonic Distortion in Pipelined ADCs , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] P. Hurst,et al. A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.
[6] Un-Ku Moon,et al. A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR , 2005, IEEE Journal of Solid-State Circuits.
[7] S. H. Lewis,et al. An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration , 2001 .
[8] Ya-Lun Yang,et al. A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[9] Un-Ku Moon,et al. Background calibration techniques for multistage pipelined ADCs with digital redundancy , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[10] Mohammad Taherzadeh-Sani,et al. Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[11] I. Galton,et al. A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.
[12] Nan Sun,et al. Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.