IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chip level MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm.

[1]  Yu Hu,et al.  Simultaneous test pattern compaction, ordering and X-filling for testing power reduction , 2009, 2009 10th International Symposium on Quality Electronic Design.

[2]  Robert K. Brayton,et al.  Using simulation and satisfiability to compute flexibilities in Boolean networks , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Shi-Jie Wen,et al.  Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[4]  R. Harboe-Sorensen,et al.  Heavy ion characterization of SEU mitigation methods for the Virtex FPGA , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[5]  James V. Jones.  Integrated Logistics Support Handbook , 1995 .

[6]  Hamid Savoj,et al.  Don't cares in multi-level network optimization , 1992 .

[7]  Jason Cong,et al.  LUT-based FPGA technology mapping for reliability , 2010, Design Automation Conference.

[8]  Yu Hu,et al.  Rewiring for robustness , 2010, Design Automation Conference.

[9]  Yu Hu,et al.  Robust FPGA resynthesis based on fault-tolerant Boolean matching , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[10]  Yu Hu,et al.  IPR: In-Place Reconfiguration for FPGA fault tolerance , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[11]  Lei He,et al.  In-place decomposition for robustness in FPGA , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  K. McMillan.  Don’t-Care Computation using k-clause Approximation , 2005 .

[13]  Robert K. Brayton,et al.  SAT-based complete don't-care computation for network optimization , 2005, Design, Automation and Test in Europe.

[14]  Robert K. Brayton,et al.  Scalable don't-care-based logic optimization and resynthesis , 2009, FPGA '09.

[15]  Yong-surk Lee,et al.  Single error correction, double error detection and double adjacent error correction with no mis-correction code , 2013, IEICE Electron. Express.