Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting

Most computer-aided design frameworks rely upon building BDD representations from netlist descriptions. In this paper, we present efficient algorithms for building BDDs from netlists. First, we introduce a dynamic scheduling algorithm for building BDDs for gates of the netlist, using an efficient hybrid of depth- and breadth-first traversal, and constant propagation. Second, we introduce a dynamic algorithm for optimally leveraging constraints and invariants as don't-cares during the building of BDDs for intermediate gates. Third, we present an automated and complete case splitting approach which is triggered by resource bounds. Unlike prior work in case splitting which focused upon variable cofactoring, our approach leverages the full power of our don't-caring solution and intelligently selects arbitrary functions to apply as constraints to maximally reduce peak BDD size while minimizing the number of cases to be explored. While these techniques may be applied to enhance the building of BDDs for arbitrary applications, we focus on their application within cycle-based symbolic simulation. Experiments confirm the effectiveness of these synergistic approaches in enabling optimal BDD building with minimal resources.

[1]  Jacob A. Abraham,et al.  Property Checking via Structural Analysis , 2002, CAV.

[2]  George J. Milne,et al.  Correct Hardware Design and Verification Methods , 2003, Lecture Notes in Computer Science.

[3]  Robert P. Kurshan,et al.  Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach , 2014 .

[4]  Jason Baumgartner,et al.  Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies , 2005, CHARME.

[5]  Olivier Coudert,et al.  Verification of Synchronous Sequential Machines Based on Symbolic Execution , 1989, Automatic Verification Methods for Finite State Systems.

[6]  David R. O'Hallaron,et al.  Space- and time-efficient BDD construction via working set control , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

[7]  Chris Wilson,et al.  Symbolic Simulation with Approximate Values , 2000, FMCAD.

[8]  Joseph Sifakis,et al.  Automatic Verification Methods for Finite State Systems , 1989, Lecture Notes in Computer Science.

[9]  Fabio Somenzi,et al.  CirCUs: A Satisfiability Solver Geared towards Bounded Model Checking , 2004, CAV.

[10]  Jason Baumgartner,et al.  Scalable Automated Verification via Expert-System Guided Transformations , 2004, FMCAD.

[11]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[12]  Hiroyuki Ochi,et al.  Breadth-first manipulation of very large binary-decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[13]  Jason Baumgartner,et al.  Automatic formal verification of fused-multiply-add FPUs , 2005, Design, Automation and Test in Europe.

[14]  Igor L. Markov,et al.  Improving the efficiency of circuit-to-BDD conversion by gate and input ordering , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[15]  Carl-Johan H. Seger,et al.  Formal verification using parametric representations of Boolean constraints , 1999, DAC '99.

[16]  Edmund M. Clarke,et al.  Counterexample-Guided Abstraction Refinement , 2000, CAV.

[17]  Daniel Kroening,et al.  A SAT-based algorithm for reparameterization in symbolic simulation , 2004, Proceedings. 41st Design Automation Conference, 2004..

[18]  Rajeev Murgai,et al.  Efficient scheduling techniques for ROBDD construction , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[19]  Valeria Bertacco,et al.  Cycle-based Symbolic Simulation of Synchronous Circuits , 1999, DAC 1999.

[20]  Geert Janssen,et al.  Design of a Pointerless BDD Package , 2022 .

[21]  Peter A. Beerel,et al.  Safe BDD minimization using don't cares , 1997, DAC.

[22]  Robert K. Brayton,et al.  High performance BDD package by exploiting memory hierarchy , 1996, DAC '96.

[23]  Carl-Johan H. Seger,et al.  Parametric Representations of Boolean Constraints. , 1999, DAC 1999.

[24]  Malay K. Ganai,et al.  Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Kunle Olukotun,et al.  Efficient state representation for symbolic simulation , 2002, DAC '02.