Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures

Reconfigurable architecture is one solution to the increasing computational requirement that often cannot be met by the low-end embedded processors. Compiling applications to such architectures involves hardware/software partitioning. To partition the applications, a set of parameters, such as the hardware execution time and hardware area consumption, is required for each application block. Quick derivation of the parameters for all the blocks is essential. Previous research has shown that the coarse-grained reconfigurable architectures are able to accelerate the applications. However, no research effort has been made to find the area and time for application blocks implemented on such architectures. In this paper we present an estimation model for the coarse-grained reconfigurable architectures implemented on FPGA platforms. The estimation model is able to quickly produce an area-time graph, which shows the area and time relationship, for each application block. The accuracy of the estimation model has been verified on real applications. Experiment shows that the estimation error for the area consumption is within 13% and the estimation error for the time is within 8%.

[1]  Masato Motomura,et al.  Efficient metrics and high-level synthesis for dynamically reconfigurable logic , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[3]  Nadia Nedjah,et al.  How many CLBs does your circuit need to be implemented? [Configurable logic blocks] , 2001, Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001.

[4]  Guy L. Curry,et al.  Solving multidimensional knapsack problems with generalized upper bound constraints using critical event tabu search , 2005, Comput. Oper. Res..

[5]  Vincent C. Li.  Tight oscillations tabu search for multidimensional knapsack problems with generalized upper bound constraints , 2005, Comput. Oper. Res..

[6]  Fadi J. Kurdahi,et al.  A comprehensive estimation technique for high-level synthesis , 1995 .

[7]  Jean Vuillemin,et al.  A reconfigurable arithmetic array for multimedia applications , 1999, FPGA '99.

[8]  Reinaldo A. Bergamaschi,et al.  Timing analysis in high-level synthesis , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[9]  Alok N. Choudhary,et al.  Accurate area and delay estimators for FPGAs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[10]  Scott A. Mahlke,et al.  Trimaran: An Infrastructure for Research in Instruction-Level Parallelism , 2004, LCPC.

[11]  Tulika Mitra,et al.  A Model for Hardware Realization of Kernel Loops , 2003, FPL.

[12]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[13]  Rudy Lauwereins,et al.  Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.

[14]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[15]  Sharad Malik,et al.  The design of dynamically reconfigurable datapath coprocessors , 2004, TECS.

[16]  André DeHon,et al.  Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density , 1996 .

[17]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[18]  William Fornaciari,et al.  An area estimation methodology for FPGA based designs at systemc-level , 2004, Proceedings. 41st Design Automation Conference, 2004..

[19]  Peter Gray,et al.  An overview of the COBRA-ABS high level synthesis system for multi-FPGA systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[20]  Fadi J. Kurdahi,et al.  Fast area estimation to support compiler optimizations in FPGA-based reconfigurable systems , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[21]  Scott A. Mahlke,et al.  PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators , 2002, J. VLSI Signal Process..

[22]  Fadi J. Kurdahi,et al.  REAL: A Program for REgister ALlocation , 1987, 24th ACM/IEEE Design Automation Conference.

[23]  Anne Elisabeth Haxthausen,et al.  LYCOS: the Lyngby Co-Synthesis System , 1997, Des. Autom. Embed. Syst..

[24]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[25]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.