Efficient Runtime Frame ECC Recomputation for Reliable Task Execution on Xilinx FPGAs

Many beneficial techniques in reconfigurable computing including clock management, communication and relocation sometimes rely on runtime editing of configuration bitstream. However, there is a major reliability issue with editing the content of the configuration memory of a design in runtime, especially for safety critical applications as these designs rely on using the frame Error Correcting Code (ECC) in the bitstream to track un-wanted bit flips. Hence, it is necessary that the process of editing configuration bitstream be accompanied by re-computing the Frame ECC. In this paper, we present an efficient implementation of a runtime re-computation of frame ECC for Xilinx FPGA configuration bitstream. A re-computation engine makes it possible to carry out desired editing to a design bitstream in runtime without losing the protection offered by the soft error mitigation (SEM) mechanisms. The implementation occupies only 364 LUTs, 193 flip flops and 3 lS-Kb BRAM on the Xilinx xc7a35tcpg236–1 chip and has a Iatency of only 104 clock cycles for each frame. We have shown that the Iatency does not introduce any delay to task configuration if the Frame ECC engine and the configuration controller are enabled at the same time. We have tested the scheme by successfully updating the clock frequency of a design protected by SEM mechanism in runtime, while the design was still able to detect and recover from soft errors.