RF to digital direct conversion receiver using PLL-/spl Sigma///spl Delta/ architecture: possibilities and problems

The possibilities and problems of using PLL-/spl Sigma///spl Delta/ architecture to construct a RF to digital direct conversion receiver is investigated by taking different kinds of noises into consideration. The contribution of each noise in the receiver is analyzed by deriving the output response of the receiver in the z-domain and performing time-domain simulation. Some preliminary results are given.

[1]  Asad A. Abidi,et al.  Low-power radio-frequency ICs for portable communications , 1995, Proc. IEEE.

[2]  John J. Paulos,et al.  An analysis of nonlinear behavior in delta-sigma modulators , 1987 .

[3]  Roland E. Best.  Phase-Locked Loops , 1984 .

[4]  Ian Galton,et al.  Combined RF phase extraction and digitization , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[5]  Ian Galton.  Higher-order delta-sigma frequency-to-digital conversion , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[6]  Ian Galton.  A practical second-order delta-sigma frequency-to-digital converter , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[7]  Gabor C. Temes,et al.  Oversampling Delta Sigma Data Converters , 1991 .

[8]  Gabor C. Temes,et al.  Oversampling delta-sigma data converters : theory, design, and simulation , 1992 .