Symbolic minimization of multilevel logic and the input encoding problem
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[1] Robert K. Brayton,et al. MIS-MV: optimization of multi-level logic with multiple-values inputs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[2] Tiziano Villa,et al. A framework for satisfying input and output encoding constraints , 1991, 28th ACM/IEEE Design Automation Conference.
[3] Albert R. Wang,et al. Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[4] Gary D. Hachtel,et al. BOLD: The Boulder Optimal Logic Design system , 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.
[5] Alberto L. Sangiovanni-Vincentelli,et al. MUSTANG: state assignment of finite state machines targeting multilevel logic implementations , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] G. De Micheli. Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] Robert K. Brayton,et al. Algorithms for discrete function manipulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[8] Louise H. Trevillyan,et al. A global approach to circuit size reduction , 1988 .
[9] Yahiko Kambayashi,et al. The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.
[10] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[11] Alberto L. Sangiovanni-Vincentelli,et al. Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Alberto Sangiovanni-Vincentelli,et al. Logic synthesis for vlsi design , 1989 .
[13] Robert K. Brayton,et al. Optimal State Assignment for Finite State Machines , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Melvin A. Breuer,et al. Generation of optimal code for expressions via factorization , 1969, CACM.
[16] C. D. Gelatt,et al. Optimization by Simulated Annealing , 1983, Science.
[17] Seiyang Yang,et al. Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] Robert K. Brayton,et al. Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] A. Richard Newton,et al. MUSE: a multilevel symbolic encoding algorithm for state assignment , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Gary D. Hachtel,et al. Verification algorithms for VLSI synthesis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] James H. Tracey. Internal State Assignments for Asynchronous Sequential Machines , 1966, IEEE Trans. Electron. Comput..
[22] Tiziano Villa,et al. NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.
[23] Maciej J. Ciesielski,et al. A unified approach to input-output encoding for FSM state assignment , 1991, 28th ACM/IEEE Design Automation Conference.