Efficient realization of reconfigurable FIR filter using the new coefficient representation

In this paper, efficient reconfigurable finite-impulse response (FIR) filter architecture is presented based on a new coefficient representation method. The proposed binary signed subcoefficient method increases the common subexpressions and decrease the hardware usage and complexity. FPGA synthesis results of the designed two reconfigurable FIR filter architectures show that 33% and 27% reductions in the resources usage are achievable over the previously reported two state of the art reconfigurable architectures.

[1]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[2]  O. Vainio,et al.  Comparison of programmable FIR filter architectures for low power , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[3]  R. Hartley.  Subexpression sharing in filters using canonic signed digit multipliers , 1996 .

[4]  K. Roy,et al.  Computation sharing programmable FIR filter for low-power and high-performance applications , 2004, IEEE Journal of Solid-State Circuits.

[5]  Tzi-Dar Chiueh,et al.  A Low-Power Digit-Based Reconfigurable FIR Filter , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Jie Zhang,et al.  A high-speed, programmable, CSD coefficient FIR filter , 2002, IEEE Trans. Consumer Electron..

[7]  A. Prasad Vinod,et al.  New Reconfigurable Architectures for Implementing FIR Filters With Low Complexity , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Ali Aghagolzadeh,et al.  A new hardware efficient, low power FIR digital filter implementation approach , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.