10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter

Ring PLLs play an important role in mobile baseband applications. In cases where fine frequency resolution and low jitter are both needed, wideband fractional-N PLL architectures with quantization noise (Q-noise) cancellation are preferred. Phase interpolators (PI) are widely used in recent literature [1-3]. Although the Q-noise is reduced, decreasing supply voltages severely limit the linearity and noise of PI. In this paper, we present a switched-capacitor loop filter (SCLF) to solve this problem. The developed SCLF with correlated double sampling (CDS) keeps the output of the charge pump (CP) near-ground to improve its noise, linearity, and power-supply rejection ratio (PSRR). Furthermore, a calibrated 2b ADC is used to realize type-II operation.

[1]  Che-Fu Liang,et al.  A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Yun-Shiang Shu.  A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[3]  Jae-Yoon Sim,et al.  A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering , 2011, 2011 IEEE International Solid-State Circuits Conference.

[4]  Ping-Ying Wang,et al.  15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[5]  Ahmed Elkholy,et al.  A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.