Architecture and design flow for a debug event distribution interconnect

In this paper, we describe and analyze the architecture of the proposed Debug Event Distribution Interconnect (EDI). The EDI transmits debug events, which are 1-bit signals, between debug entities in different areas of the Network-on-Chip based Multi-Processor System-on-Chip. The EDI replicates the NoC topology with an EDI node instantiated for each underlying NoC data module. Contention in the EDI node is handled by replicating the EDI in layers. The EDI generation is automatic, and uses as input the cross-triggering patterns that are not required to follow the communication patterns in the NoC. The generation and routing tool is also presented in this paper. The EDI is evaluated with four different implementations varying complexity and handling of contention. The area of a single EDI Layer is around 0.9% of the area occupied by the tested NoCs, using the lower area implementation. These results show that the proposed implementation of the EDI incurs low cost on the overall system.

[1]  Qiang Xu,et al.  A Multi-Core Debug Platform for NoC-Based Systems , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Kees G. W. Goossens,et al.  A high-level debug environment for communication-centric debug , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[3]  Kees G. W. Goossens,et al.  Interactive Debug of SoCs with Multiple Clocks , 2011, IEEE Design & Test of Computers.

[4]  Ieee Standard Test Access Port and Boundary-scan Architecture Ieee-sa Standards Board , 2001 .

[5]  Alejandro Duran,et al.  The Intel® Many Integrated Core Architecture , 2012, 2012 International Conference on High Performance Computing & Simulation (HPCS).

[6]  Nikil Dutt,et al.  On-Chip Interconnect with aelite: Composable and Predictable Systems , 2010 .

[7]  Kees G. W. Goossens,et al.  A distributed architecture to check global properties for post-silicon debug , 2010, 2010 15th IEEE European Test Symposium.

[8]  Qiang Xu,et al.  In-band Cross-Trigger Event Transmission for Transaction-Based Debug , 2008, 2008 Design, Automation and Test in Europe.

[9]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[10]  Gianluca Palermo,et al.  A monitoring system for NoCs , 2010, NoCArc '10.

[11]  Kees G. W. Goossens,et al.  Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective , 2006, 2006 International Symposium on Industrial Embedded Systems.

[12]  Kees G. W. Goossens,et al.  NoC monitoring: impact on the design flow , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[13]  Michael Barbehenn,et al.  A Note on the Complexity of Dijkstra's Algorithm for Graphs with Weighted Vertices , 1998, IEEE Trans. Computers.

[14]  Tien-Fu Chen,et al.  NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems , 2012, IEEE Transactions on Computers.

[15]  Kees G. W. Goossens,et al.  Transaction-Based Communication-Centric Debug , 2007, First International Symposium on Networks-on-Chip (NOCS'07).