Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects

High-performance strained Silicon-On-Insulator (sSOI) nanowires (NW) with gate width (WNW) and length (L<sub>G</sub>) scaled down to 10nm are presented. For the first time, effectiveness of sSOI substrates is demonstrated for ultra-scaled N-FET NW (L<sub>G</sub>=10nm) with an outstanding I<sub>ON</sub> current (I<sub>ON</sub>=1420μA/μm at IOFF=300nA/μm) and an excellent electrostatic immunity (DIBL=82mV/V). P-FET NW performance enhancement is achieved using in-situ HCl+GeH<sub>4</sub> etching and selective epitaxial growth of boron-doped Si<sub>0.7</sub>Ge<sub>0.3</sub> for the formation of recessed Sources/Drains (S/D). We show an I<sub>ON</sub> improvement up to +100% induced by recessed SiGe S/D for L<sub>G</sub>=13nm P-FET NW. Finally, size- and orientation-dependent strain impact on short channel performances is discussed. <;110> Si NWs provide the best opportunities for strain engineering.