Embedded bus switches on 3D data bus for critical access time reduction

Data are frequently running on the 3D data bus of a stacked-layer chip at different timing periods, but all the local data buses are not always used at each timing period. In this paper, we proposed an algorithm based on embedded bus switches for the critical access time reduction on a 3D data bus. The embedded bus switches can isolate those unnecessary local bus capacitive loadings whereas data are transferred from a local data bus to other data bus at a timing period and their access time can be obviously reduced. Moreover, the algorithm inserts signal repeaters into their bus wires located on the current critical path and tunes their sizes to minimize the critical access time. The tuning procedure is repeated until no additional improvement. Experimental results show that the critical access time on a 3D data bus with embedded bus switches is reduced up to 53.18% on average. In advance, the critical access time with inserted signal repeaters can be reduced up to 76.65% on average.